Evaluation and simulation of event building techniques for a detector at the LHC

The main objectives of future experiments at the Large Hadron Collider are the search for the Higgs boson (or bosons), the verification of the Standard Model and the search beyond the Standard Model in a new energy range up to a few TeV. These experiments will have to cope with unprecedented high data rates and will need event building systems which can offer a bandwidth of 1 to 100GB/s and which can assemble events from 100 to 1000 readout memories at rates of 1 to 100kHz. This work investigates the feasibility of parallel event building sys- tems using commercially available high speed interconnects and switches. Studies are performed by building a small-scale prototype and by modelling this proto- type and realistic architectures with discrete-event simulations. The prototype is based on the HiPPI standard and uses commercially available VME-HiPPI interfaces and a HiPPI switch together with modular and scalable software. The setup operates successfully as a parallel event building system of limited size in different configurations, with different input data and different data flow management schemes. Realistic parameters of 40MB/s for the link speed and of 100us for the overhead have been measured and the total throughput is scalable with the number of destinations. The prototype measure- ments lead to a parametrized model of a parallel event building system which is implemented in a simulation program. This is used to simulate large-scale systems including a realistic model of the ATLAS event building system with realistic event size distributions from off-line simulations. The influence of different parameters and the scaling behaviour are investigated. Different data flow management schemes for destination assignment and traffic shaping are studied as well as a two-stage event building system

The Trigger Menu Handler of the ATLAS Level-1 Central Trigger Processor

The role of the Central Trigger Processor (CTP) in the ATLAS Level-1 trigger is to combine information from the calorimeter and muon trigger processors, as well as from other sources, e.g. calibration triggers, and to make the final Level-1 decision. The information sent to the CTP consists of multiplicity values for a variety of pT thresholds, and of flags for ET thresholds. The algorithm used by the CTP to combine the different trigger inputs allows events to be selected on the basis of menus. Different trigger menus for different run conditions have to be considered. In order to provide sufficient flexibility and to fulfil the required low latency, the CTP will be implemented with look-up tables and programmable logic devices. The trigger menu handler is the tool that translates the human-readable trigger menu into the configuration files necessary for the hardware, stores several prepared configurations and down-loads them into the hardware on request. An automatic compiler for the trigger menu and a prototype of the trigger menu handler have been implemented

A configuration system for the ATLAS trigger

The ATLAS detector at CERN's Large Hadron Collider will be exposed to proton-proton collisions from beams crossing at 40 MHz that have to be reduced to the few 100 Hz allowed by the storage systems. A three-level trigger system has been designed to achieve this goal. We describe the configuration system under construction for the ATLAS trigger chain. It provides the trigger system with all the parameters required for decision taking and to record its history. The same system configures the event reconstruction, Monte Carlo simulation and data analysis, and provides tools for accessing and manipulating the configuration data in all contexts.Comment: 4 pages, 2 figures, contribution to the Conference on Computing in High Energy and Nuclear Physics (CHEP06), 13.-17. Feb 2006, Mumbai, Indi

A Demonstrator for the ATLAS Level-1 Muon to Central Trigger Processor Interface (MUCTPI)

The Level-1 Muon Trigger Interface (MUCTPI) to the Central Trigger Processor (CTP) receives trigger information from the detector- specific logic of the muon trigger. This information contains up to two muon-track candidates per sector. The MUCTPI combines the information of all sectors and calculates total multiplicity values for each of six programmable pT thresholds. It avoids double counting of single muons by taking into account the fact that some of the trigger sectors overlap. The MUCTPI sends the multiplicity values to the CTP which takes the final Level-1 decision. For every Level-1 Accept (L1A) the MUCTPI sends region-of-interest (RoI) information to the Level-2 trigger and event data to the data acquisition system. A demonstrator of the MUCTPI has been built which has the performance of the final system but has limited flexibility for calculating the overlap. The functionality and the performance of the demonstrator are presented

Antimatter and Matter Production in Heavy Ion Collisions at CERN (The NEWMASS Experiment NA52)

Besides the dedicated search for strangelets NA52 measures light (anti)particle and (anti)nuclei production over a wide range of rapidity. Compared to previous runs the statistics has been increased in the 1998 run by more than one order of magnitude for negatively charged objects at different spectrometer rigidities. Together with previous data taking at a rigidity of -20 GeV/c we obtained 10^6 antiprotons 10^3 antideuterons and two antihelium3 without centrality requirements. We measured nuclei and antinuclei (p,d,antiprotons, antideuterons) near midrapidity covering an impact parameter range of b=2-12 fm. Our results strongly indicate that nuclei and antinuclei are mainly produced via the coalescence mechanism. However the centrality dependence of the antibaryon to baryon ratios show that antibaryons are diminished due to annihilation and breakup reactions in the hadron dense environment. The volume of the particle source extracted from coalescence models agrees with results from pion interferometry for an expanding source. The chemical and thermal freeze-out of nuclei and antinuclei appear to coincide with each other and with the thermal freeze-out of hadrons.Comment: 12 pages, 8 figures, to appear in the proceedings of the conference on 'Fundamental Issues in Elementary Matter' Bad Honnef, Germany, Sept. 25-29, 200

Framework for Testing and Operation of the ATLAS Level-1 MUCTPI and CTP

The ATLAS Level-1 Muon-to-Central-Trigger-Processor Interface (MUCTPI) receives information on muon candidates from the muon trigger sectors and sends multiplicity values to the Central Trigger Processor (CTP). The CTP receives the multiplicity values from the MUCTPI and combines them with information from the calorimeter trigger and other triggers of the experiment and makes the final Level-1 decision. The MUCTPI and CTP are housed in two 9U VME64x crates and are made of nine different types of custom designed modules. This paper will present the framework which is used for debugging, commissioning and operation of all modules of the MUCTPI and CTP. Testing of the modules has been considered right from design. Most types of modules contain diagnostic memories at the input of the module which can be used to capture incoming data or to inject data into the module. Testing of the modules can be achieved by capturing data at input of a down-stream module, by reading out data from a monitoring buffer, or by reading out monitoring counters. A layered software framework using C++ has been developed for configuring and controlling all modules and for testing them independently or grouped into complete subsystems. The lowest level uses the ATLAS VME library and driver. At the next higher level, a compiler translates a description of the VME registers from XML to C++ code. This code together with existing code for some components, e.g. HPTDC, DELAY25, and JTAG, is combined to the lowlevel library of the module. A menu program provides access to all methods of the module low-level library. Generators create data for the test memories. Simulators calculate expected results. Generators, simulators and the low-level library are combined to a suite of test programs which cover the full functionality of the MUCTPI and CTP. The low-level library is also used by the control and monitoring programs which integrate the sub-systems into the ATLAS experiment control and monitoring framework

The Octant Module of the ATLAS Level-1 Muon to Central Trigger Processor Interface

The Muon to Central Trigger Processor Interface (MUCTPI) of the ATLAS Level-1 trigger receives data from the sector logic modules of the muon trigger at every bunch crossing and calculates the total multiplicity of muon candidates, which is then sent to the Central Trigger Processor where the final Level-1 decision is taken. The MUCTPI system consists of a 9U VME crate with a special backplane and 18 custom designed modules. We focus on the design and implementation of the octant module (MIOCT). Each of the 16 MIOCT modules processes the muon candidates from 13 sectors of one half-octant of the detector and forms the local muon candidate multiplicities for the trigger decision. It also resolves the overlaps between chambers in order to avoid double-counting of muon candidates that are detected in more than one sector. The handling of overlapping sectors is based on Look-Up-Tables (LUT) for maximum flexibility. The MIOCT also sends the information on the muon candidates over the custom backplane via the Readout Driver module to the Level-2 trigger and the DAQ systems when a Level-1 Accept is received. The design is based on state-of-the-art FPGA devices and special attention was paid to low-latency in the data transmission and processing

The ATLAS Level-1 Muon to Central Trigger Processor Interface

The Muon to Central Trigger Processor Interface (MUCTPI) is part of the ATLAS Level-1 trigger system and connects the output of muon trigger system to the Central Trigger Processor (CTP). At every bunch crossing (BC), the MUCTPI receives information on muon candidates from each of the 208 muon trigger sectors and calculates the total multiplicity for each of six transverse momentum (pT) thresholds. This multiplicity value is then sent to the CTP, where it is used together with the input from the Calorimeter trigger to make the final Level-1 Accept (L1A) decision. In addition the MUCTPI provides summary information to the Level-2 trigger and to the data acquisition (DAQ) system for events selected at Level-1. This information is used to define the regions of interest (RoIs) that drive the Level-2 muontrigger processing. The MUCTPI system consists of a 9U VME chassis with a dedicated active backplane and 18 custom designed modules. The design of the modules is based on state-of-the-art FPGA devices and special attention was paid to low-latency in the data transmission and processing. We present the design and implementation of the final version of the MUCTPI. A partially populated MUCTPI system is already installed in the ATLAS experiment and is being used regularly for commissioning tests and combined cosmic ray data taking runs

Hardware studies for the upgrade of the ATLAS Central Trigger Processor

The ATLAS Central Trigger Processor (CTP) is the final stage of the first level trigger system which reduces the collision rate of 40 MHz to a level-1 event rate of 75 kHz. The CTP makes the Level-1 trigger decision based on multiplicity values of various transverse-momentum thresholds as well as energy information received from the calorimeter and muon trigger sub-systems using programmable selection criteria. In order to improve the rejection rate for the first phase of the luminosity upgrade of the LHC to 3∙1034 cm-2 s-1 planned for 2015, one of the options being studied consists of adding a topological trigger processor, using Region-Of-Interest information from the calorimeter and potentially also the muon trigger. This will require an upgrade of the CTP in order to accommodate the additional trigger inputs. The current CTP system consists of a 9U VME64x crate with 11 custom designed modules where the functionality is largely implemented in FPGAs. The constraint for the upgrade study presented here was to reuse the existing hardware as much as possible. This is achieved by operating the backplane at twice the design frequency and required developing new FPGA firmware for several of the CTP modules. We present the design of the newly developed firmware for the input, monitoring and core modules of the CTP as well as results from initial tests of the upgraded system